A combination of logic gates is as shown in t | vedclass

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(A) Given inputs are $P = 0$,$Q = 1$,$R = 0$,and $S = 1$.$1$. The output $X$ is obtained from an $AND$ gate with inputs $P$ and $Q$. Thus,$X = P \cdot

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$0, 1, 0$

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(A) Given inputs are $P = 0$,$Q = 1$,$R = 0$,and $S = 1$.$1$. The output $X$ is obtained from an $AND$ gate with inputs $P$ and $Q$. Thus,$X = P \cdot Q = 0 \cdot 1 = 0$.$2$. The input to the $NOT$ gate is the output of an $AND$ gate with inputs $R$ and $S$. Let this be $W$. So,$W = R \cdot S = 0 \cdot 1 = 0$. The output $Y$ is the $NOT$ of $W$,so $Y = \overline{W} = \overline{0} = 1$.$3$. The output $Z$ is obtained from a $NOR$ gate with inputs $X$ and $Y$. Thus,$Z = \overline{X + Y} = \overline{0 + 1} = \overline{1} = 0$.Therefore,the outputs are $X = 0$,$Y = 1$,and $Z = 0$.

$A$ combination of logic gates is as shown in the figure. $P$,$Q$,$R$,and $S$ are the inputs and $X$,$Y$,and $Z$ are outputs. When inputs $P$ and $R$ are 'low' $(0)$ and $Q$ and $S$ are 'high' $(1)$,the outputs $X$,$Y$,and $Z$ are respectively:

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