The combination of NAND gates is shown in fig | vedclass

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(B) In figure $(I)$,the inputs to the first two $NAND$ gates are both $0$. Since a $NAND$ gate with both inputs tied together acts as a $NOT$ gate,the

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$0, 1$

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(B) In figure $(I)$,the inputs to the first two $NAND$ gates are both $0$. Since a $NAND$ gate with both inputs tied together acts as a $NOT$ gate,the output of each is $\overline{0} = 1$. These two $1$s are then fed into the final $NAND$ gate. The output is $\overline{1 \cdot 1} = \overline{1} = 0$.In figure $(II)$,the inputs are $1$ and $1$. The first $NAND$ gate gives an output of $\overline{1 \cdot 1} = 0$. This $0$ is then fed into the second $NAND$ gate (which acts as a $NOT$ gate because its inputs are tied together),resulting in an output of $\overline{0} = 1$.Thus,the outputs are $0$ and $1$ respectively.

The combination of $NAND$ gates is shown in figures $(I)$ and $(II)$. For the given inputs,the outputs in both the combinations are respectively.

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